Integrated Circuit (IC) Layout and Mask Design Engineer
 MIT Lincoln Laboratory | |
tuition reimbursement, 401(k)
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 United States, Massachusetts, Lexington | |
| 244 Wood Street (Show on map) | |
 Nov 25, 2024 | |
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Apply now Date: Nov 8, 2024 Location: Company: MIT Lincoln Laboratory's Advanced Technology Division develops advanced materials, devices, and subsystems that have broad impact on U.S. Government, industry, and academia. The Division has made a wide range of important contributions during the Laboratory's 70+ year history, including development of bulk and epitaxial crystal growth, charge-coupled device (CCD) imagers, 193-nm lithography, fully depleted silicon-on-insulator (FDSOI) CMOS electronics, semiconductor diode lasers and amplifiers, superconducting electronics and quantum bit (qubit) devices, and photonic integrated circuits (PICs). To enable this advanced technology development, the Laboratory has implemented vertically integrated in-house resources to facilitate design, lithographic mask layout, material growth and characterization, fabrication (e.g., silicon, compound-semiconductor, wafer bonding, flip-chip hybrid), packaging, and testing of electronic and photonic circuits. These in-house resources are used to fabricate a variety of devices and circuits including lasers, waveguide photodetectors, optical modulators, and CMOS and cryogenic electronics with applications in quantum computing, atomic systems, advanced laser sources, microwave photonics, communications, sensing, and other areas of interest to the U.S. Government, industry, and academia. Fabrication resources include: Job Description
The candidate will work as a member of a multi-disciplinary team responsible for the design and layout of lithographic masks for silicon-based, compound-semiconductor, and heterogeneous/hybrid fabrication processes, especially those for photonic integrated circuits (PICs). The candidate may also work on masks for superconducting qubit and trapped-ion qubit quantum computing, radiation-hard CMOS, and other emerging integrated circuit technologies. The engineer will work in the Cadence environment, with which they should be fluent, and will have responsibility for the full layout project from basic layout cell creation to final tapeout. Key tasks will include coding layout pcells; and laying out devices, test structures, systems, and full mask reticles based on input from device and process designers. They will also be responsible for working with the layout team to update and maintain a device pcell library. Required Qualifications
* There is no degree requirement for this position Preferred Qualifications: At MIT Lincoln Laboratory, our exceptional career opportunities include many outstanding benefits to help you stay healthy, feel supported, and enjoy a fulfilling work-life balance. Benefits offered to employees include:
Please visit our Benefits page for more information. As an employee of MIT, you can also take advantage ofother voluntary benefits, discounts and perks. Selected candidate will be subject to a pre-employment background investigation and must be able to obtain and maintain a Secret level DoD security clearance. MIT Lincoln Laboratory is an Equal Employment Opportunity (EEO) employer. All qualified applicants will receive consideration for employment and will not be discriminated against on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, veteran status, disability status, or genetic information; U.S. citizenship is required. Requisition ID: 41417 #LI-CA1
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