Principal IC System Architect

The IC system architect is responsible for defining the next generation of high performance sensor circuits, including system level signal analysis, optimization of the analog and digital boundary in mixed-signal circuits, and modeling and simulation strategies for those circuits. The ideal candidate has a deep understanding of chip-level system design, signal processing, power-performance tradeoffs, and modeling at various levels of abstraction. This role will require collaboration with multidisciplinary teams including analog and digital circuit designers, verification engineers, system engineers, and validation engineers.

• Define and document the system-level architecture for complex ICs that integrate sensor, analog, and digital components.
• Lead system-level simulations and feasibility studies to evaluate design tradeoffs and performance targets.
• Develop and maintain behavioral and functional models at various abstraction levels for both analog and digital domains.
• Participate in IC validation, debug, and performance correlation to ensure models accurately represent silicon behavior.
• Creatively innovate and solve new customer requirements, develop next generation IP, and file patents.
• Generate detailed documentation, including architectural and concept reviews, design gate reviews, internal design documents, and test requirements.
• Provide technical leadership and mentor junior engineers on system-level modeling and design best practices.

• MS in Electrical Engineering with 15 years of experience or PhD in Electrical Engineering with 12 years of experience, with an emphasis in mixed signal integrated circuit design or a similar specialty.
  
  

• Experience with technical leadership in mixed signal IC Design, block level specifications, simulation, modelling, optimizing layout for performance, etc.
• "Expert level" transistor level design knowledge and experience of standard analog building blocks including bandgap references, current references, OPAMPs, LDOs, charge pumps, and switched-capacitor circuits. Knowledge of ADC topologies and design is a plus.
• Experience in RTL-level digital design including combinational and sequential digital designs, clock domains, and digital/analog interfaces.
• Excellent communication skills (both oral and written) are required, as customer level technical interface and design team leadership are necessary under pressure situations.
• Experience with relevant CAD tools (including Cadence Virtuoso, SPICE, Xcelium, etc.)
• Proficiency with modeling tools, for example, Verilog-AMS, MATLAB, and/or SystemVerilog.
• PPD and SPAD optical sensor design and modeling experience is a plus.