Emulation Lead Engineer

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

• Define and execute emulation strategies and test plansfor complex connectivity silicon, including ODSP, PCIe/CXL retimers, highspeed Ethernet PHYs, and AEC/AOC enablement devices, using platforms such as Palladium, Veloce, and Zebu.
• Work with project leadership and crossfunctional teams to define emulation hardware and software requirements, including platform configurations, transactors, speed bridges, protocol adapters, and firmware/software stacks.
• Collaborate closely with EDA and emulation hardware vendorsto enable new platforms, maintain tool ecosystems, and drive debug and resolution of hardware, software, and model issues.
• Develop HW/SW enablement flows and toolsto accelerate RTL validation and improve emulation model usability for early firmware, driver, and system software development.
• Interface with presilicon validation, architecture, design, firmware, and postsilicon teamsto optimize validation methodologies and improve overall emulation efficiency.
• Build and maintain automation flows, scripts, and infrastructureto improve productivity, scalability, and utilization of emulation environments.

What We're Looking For

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science and a related field with 10+ years of relevant experience, or a Master's/PhD with 5+ years of experience.
• Strong handson experiencewith one or more SoC emulation platforms(Palladium, Veloce, Zebu), including building and maintaining largescale emulation models.
• Proven background in test planning, simulation, and debugin Verilog/SystemVerilogenvironments.
• Proven experience with SoC development flows, emulationbased debug, and systemlevel validation.
• Strong scripting and automation skillsusing Python, Perl, Tcl, and UNIX shell.
• Ability to work effectively across global, crossfunctional teamsand communicate clearly with design, validation, firmware, and vendor partners.

• Experience with emulation of networking devices or mixedsignal designs, including systems containing PHY or Layer2/Layer3 functionality.
• Experience with connectivityfocused silicon, such as:
  • Optical DSPs (ODSP)
  • PCIe/CXL retimers
  • Highspeed Ethernet PHYs
  • AEC/AOC enablement devices
• Familiarity with firmware or software bringupusing emulation platforms.
• Prior experience enabling or scaling emulation infrastructureacross multiple projects or product lines.

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.