Senior Staff Engineer, Design Verification

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

Develop verification plans for the IP in complex designs. Analyze functional coverage metrics, code coverage and toggle coverage to ensure that verification environment exercises all aspects of the design, including statements, branches, conditions, and expression. Collaborate with design and verification teams to plan the verification strategy for the given IPs. Write block level test plans to verify the functionality of a block or subsystem. Define verification goals, scope, methodologies, and metrics for measuring effectiveness and vertical scalability. Develop UVM environments and tests which comply with Marvell coding guidelines. Create and maintain System Verilog/UVM test benches for functional verification, including testcase development, sequences, drivers, monitors, scoreboard, and verification environment. Help write scripts as needed to automate tasks. Write functional coverage items and close coverage buckets. Help to monitor regressions and triage as needed. Assist in checklist closure. Assist in mentoring Interns and junior team members.

What We're Looking For

Master's or foreign equivalent degree in Electrical/Electronic Engineering, Computer Science/Engineering, or a related field and three (3) years of experience in the job offered or related occupation.

Experience must include three (3) years with each of the following:

* Semiconductor ASIC design/verification methodologies and flows.
* Verilog, System Verilog, UVM.
* Programming skills including object-oriented programming.
* Digital logic design and verification.
* Device reset architecture, Device clocking, FUSE, SerDes, Ethernet, and PCIe.
* PB (Partition builder tool).
* Bash, Perl, Python, and C.
* IEEE standard ethernet protocol and AMBA/APB protocol.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.