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Advanced Silicon Technology Delivery Lead

Advanced Micro Devices, Inc.
$221,360.00/Yr.-$332,040.00/Yr.
United States, California, San Jose
2100 Logic Drive (Show on map)
Oct 10, 2025


WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE:

We are seeking an experienced and technically driven professional to lead technology enablement and foundry interface activities for advanced silicon nodes (e.g., N3/N2 and beyond). The candidate will work cross-functionally with internal design, architecture, and product engineering teams to ensure that power, performance, and area (PPA) objectives are achieved in alignment with product requirements.

THE PERSON:

This role requires a candidate with a proactive mindset and the ability to work independently, while also demonstrating strong collaboration skills within a team-oriented environment.

KEY RESPONSIBILITIES:

  • Collaborate with internal design, architecture, and product teams to align foundry process technologies with product performance, power, and area (PPA) targets.
  • Serve as a technical liaison with external foundries to support process definition, silicon debug, and technology ramp readiness.
  • Support technology-to-product issue resolution, proposing data-driven solutions for device, interconnect, or yield challenges..
  • Coordinate with reliability and packaging teams to evaluate and mitigate Si-package interaction risks during early product development.
  • Prepare and present concise technical reports summarizing analysis results, foundry updates, and cross-functional recommendations.

PREFERRED EXPERIENCE:

  • Semiconductor experience in process integration, DTCO (design technology co-optimization, yield engineering, or foundry enablement.
  • Strong understanding of device physics, process variability, and reliability mechanisms (BTI, TDDB, EM).
  • Hands-on experience with advanced nodes (N5/N3/N2) and 3D packaging technologies (SoIC, CoWoS) is a plus.
  • Familiarity with silicon bring-up, data analysis, and yield debug methodologies.
  • Excellent communication and teamwork skills to operate effectively across internal organizations and with external partners.

EDUCATION:

Master's degree or Doctoral degree preferred in Electrical Engineering, Materials Science and Engineering, or a related field.

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

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