SoC Architecture Engineer

THE ROLE:

As a member of the Radeon Technologies Group, you will help define and deliver industry-leading SoC designs. As a Principal SoC Architect, you will lead the translation of product requirements into SoC-level architecture, collaborating with CPU, GPU, memory controller, IP and SOC design, physical design, and product engineering teams. You will own SoC-level features such as clocking, reset, power architecture, and performance planning, driving first-pass silicon success and delivering best-in-class power and performance.

THE PERSON:

A successful candidate will be a proven technical leader with deep SoC architecture expertise. You will be highly analytical, detail-oriented, and capable of influencing across multiple teams. Strong communication and collaboration skills are essential, as you will define SoC-level strategy, mentor other engineers, and align cross-functional teams toward common product goals.

KEY RESPONSIBILITIES:

• Define SoC-level architecture by translating product requirements into detailed specifications.

• Own SoC-specific elements including clocking, reset, power domains, and low-power design strategies.

• Drive the definition and implementation of SoC performance and power features to meet aggressive product targets.

• Partner with CPU, GPU, and memory controller IP teams to ensure architectural alignment of features and clean interoperability and integration.

• Lead cross-functional design reviews and influence decisions across design, verification, and physical implementation.

• Provide technical leadership during performance modeling, power analysis, and trade-off studies.

• Guide post-silicon bring-up efforts to validate SoC features and deliver production-quality results.

• Mentor and coach junior engineers, providing technical direction and fostering best practices in SoC design.

PREFERRED EXPERIENCE

• 10+ years of experience in SoC architecture, system design, or integration.

• Deep expertise in clocking, reset distribution, and power intent definition (UPF/CPF).

• Proven track record of low-power SoC design (clock gating, power gating, DVFS, multi-voltage domains).

• Strong understanding of CPU, GPU, and memory subsystem interfaces and integration challenges.

• Experience with SoC-level performance modeling, power analysis, and design trade-offs.

• Working knowledge of RTL design and verification flows, including integration and signoff.

• Excellent leadership, communication, and cross-team collaboration skills with the ability to influence at all levels.

• Experience leading cross-functional teams through first-pass silicon success.